1. Field of the Invention
The present invention relates to a circuit, an apparatus and a method for generating an address in a semiconductor memory testing device.
2. Description of Related Art
The circuit for generating an address is one in a semiconductor memory testing device, for generating an address signal of a memory cell to be read (read out) or to be written (written in) at a high speed, on the basis of the predetermined algorithm.
FIG. 6 is a view showing an example of a circuit 100 for generating an address according to an earlier development. In FIG. 6, the circuit 100 for generating an address comprises a counter 10 and ALU (Arithmetic and Logic Unit) 20.
The counter 10 counts the pulse number of a clock pulse signal by +1, which gives a pulse as a clock and which is inputted from the outside of the circuit 100. Thereafter, the counter 10 outputs the count number to ALU 20.
When the count number is inputted from the counter 10 to ALU 20, ALU 20 carries on the predetermined operation on the basis of the count number and a reference address inputted from the outside of the circuit 100. Thereafter, ALU 20 outputs an address signal as the result of the predetermined operation. The address signal is an address for the semiconductor memory as an object of test.
Whenever the next pulse of the clock pulse signal is inputted to the counter 10, the counter 10 counts the pulse number of the clock pulse signal and outputs the count number to ALU 20. Accordingly, whenever the count number is inputted from the counter 10 to ALU 20, ALU 20 operates the count number and outputs the address signal one after another.
That is, the circuit 100 for generating an address operates on the reference address signal according to the input of the pulse of the clock pulse signal and outputs the address signal one after another.
However, according to the circuit 100 for generating an address according to an earlier development, the counter 10 only counts the pulse number of the clock pulse signal by +1. Accordingly, it is possible to generate the only predetermined address on the basis of the reference address.
Further, when a plurality of circuits 100 are used at a plurality of steps and carry on the predetermined operation on the basis of the common clock pulse signal and the common reference address signal, each circuit 100 outputs the same address signal. Consequently, it has been difficult to generate the different addresses from one another, by a plurality of circuits 100 at the same time.
The present invention was developed in view of the above-described problems.
An object of the present invention is to provide a circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address. Another object of the present invention is to provide an apparatus for generating an address, which can generate the different addresses from one another by using a plurality of circuits described above at a plurality of steps.
In accordance with one aspect of the present invention, a circuit (for example, a circuit 200 shown in FIG. 1) for generating an address, comprises: a multiplex counter (for example, a multiplex counter 30 shown in FIG. 1) comprising a counter (for example, a counter 31 shown in FIG. 2) for counting a pulse number of a clock signal to generate a count number (for example, xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d shown in FIG. 4) represented by binary bit and a bit shift circuit (for example, a bit shift circuit 33) for shifting the count number, to generate an output count number (for example, xe2x80x9c000xe2x80x9d, xe2x80x9c010xe2x80x9d, xe2x80x9c100xe2x80x9d and xe2x80x9c110xe2x80x9d shown in FIG. 4); and an arithmetic circuit (for example, ALU 20 shown in FIG. 1) for operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.
The clock signal is a signal that gives a pulse as a clock, so that the clock signal is called a clock pulse signal in the preferred embodiment of the present invention.
According to the multiplex counter of the circuit as described above, the counter counts the pulse number of the clock signal to generate the count number represented by binary bit and the bit shift circuit shifts the count number, to generate the output count number.
Consequently, it is possible to output a plurality of types of the output count number from the multiplex counter, by changing a shift number of shifting the count number. Further, it is possible to change a count-up number of the output count number by changing the count number to the output count number.
Further, according to the arithmetic circuit of the circuit as described above, the arithmetic circuit operates the address signal to be inputted to a semiconductor memory as an object of test, on the basis of the output count number generated by shifting the count number and the reference address signal.
Consequently, it is possible to output a plurality of types of the address signal to a semiconductor memory as an object of test.
Preferably, in a circuit for generating an address, as described above, the multiplex counter (a multiplex counter 30 shown in FIG. 2) further comprises a storage unit (a register 32 shown in FIG. 2) for storing a predetermined number therein and an adder (an adder 34 shown in FIG. 2) for adding the predetermined number to the count number shifted by the bit shift circuit, to generate the output count number.
The predetermined number stored in the storage unit is not limited to a fixed number. For example, the predetermined number may be changed by an external signal or the like, as the occasion may demand.
According to the multiplex counter of the circuit as described above, for example, the adder adds the predetermined number stored in the storage unit to a free low bit occurred by shifting the count number, to generate the output count number.
Consequently, it is possible to generate the output count number having various numbers from one count number by adding the predetermined number to the count number shifted by the bit shift circuit, and it is possible to output various types of the output count number from the multiplex counter.
In accordance with another aspect of the present invention, an apparatus (an apparatus 500 shown in FIG. 3) for generating an address, comprises: a plurality of circuits (circuits 200-1 to 200-n shown in FIG. 3) as described above, wherein each circuit stores the different predetermined number from one another in the storage unit of the multiplex counter thereof (a register of each of multiplex counters 30-1 to 30-n shown in FIG. 3) and generates the different address signal from one another at the same time on the basis of the reference address signal.
According to the apparatus as described above, the predetermined number stored in the storage unit of the multiplex counter of each circuit is different from one another, so that the multiplex counter of each circuit outputs the different output count number from one another.
Consequently, it is possible for a plurality of circuits to generate the different address signals from one another at the same time on the basis of the reference address signal.
Preferably, an apparatus for generating an address, as described above, further comprises: a switching output circuit (a multiplexer 300 shown in FIG. 3) for switching a plurality of different address signals from one another, generated by a plurality of circuits at the same time, in order, to output a series of different address signals.
According to the apparatus as described above, the switching output circuit can switch a plurality of different address signals from one another, generated at the same time and output a series of different address signals. Consequently, it is possible to continuously output the different address signals from one another to a semiconductor memory.
Further, according to a change of the number of the steps of the circuits incorporated in the apparatus, the switching output circuit changes the speed of switches the address signals and outputting any one of the address signals. Consequently, it is possible to easily generate the different address signals from one another in order continuously. In this case, if the switching output circuit can operate at a high speed, it is unnecessary to change the circuits at all. As a result, it is possible to realize the circuit at a low cost.
In accordance with a further aspect of the present invention, a method for generating an address, comprises the steps of: counting a pulse number of a clock signal to generate a count number represented by binary bit; shifting the count number to generate an output count number; and operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.
Preferably, a method for generating an address, as described above, further comprises the step of: adding a predetermined number to the count number shifted, to generate the output count number.
According to the method as described above, for example, the output count number is generated by adding the predetermined number stored in the storage unit to a free low bit occurred by shifting the count number.
Consequently, it is possible to generate the output count number having various numbers from one count number by adding the predetermined number to the count number shifted by the bit shift circuit, and it is possible to output various types of the output count number.